1. Field of the Invention
The present invention relates to non-volatile semiconductor memories and, more particularly, to an electrically erasable programmable read-only memory with a large capacity.
2. Description of the Related Art
With the increasing needs for high performance and reliability of digital computer systems, development of a semiconductor memory with a large capacity which can replace an existing non-volatile data storage device for digital computer systems, such as a magnetic floppy disk unit, has been strongly demanded. A presently-available electrically erasable programmable read-only memory has technical merits such as higher reliability and a higher data write/read rate than those of a magnetic data storage device such as a floppy disk unit or a hard disk unit; however, the data storage capacity of the memory of this type is not so large as to replace the magnetic data storage device.
In a conventional electrically erasable programmable read-only memory (to be referred to as an "EEPROM" hereinafter), each memory cell is typically arranged to include two transistors. Therefore, it cannot be expected to provide a high integration density which can provide a large capacity capable of replacing peripheral data storage devices.
Recently, as a non-volatile semiconductor memory which is highly integrated and therefore has a large capacity, an erasable programmable read-only memory with a "NAND type cell" structure has been developed. A typical arrangement of a memory of this type is proposed in, for example, "A High Density EPROM Cell and Array", Symposium of VLSI Technology, Digest of Technical Papers, R. Stewart et al., May 1986, at p. 89 to 90. According to a memory device of this type, each memory cell consists of one transistor having a floating gate and a control gate, and only one contact portion is formed between an array of memory cells arranged on a substrate to constitute a "NAND cell" structure and the corresponding bit line. Therefore, a cell area with respect to the substrate can be reduced much smaller than that of a conventional EEPROM, thereby improving the integration density thereof.
However, the above EEPROM suffers from a problem of low operational reliability. In each memory cell transistor, a polycrystalline silicon insulative layer is formed between a floating gate and a control gate to insulate the two gates from each other. It is considered that film quality of the polycrystalline silicon insulative layer is much lower than that of a silicon oxide (SiO.sub.2) layer deposited on the substrate. Since carriers for data storage form an electric field between the floating and control gates and move therebetween by tunneling through the polycrystalline silicon insulative layer, characteristics of the memory cell in a data writing/erasing mode are degraded. This results in that it becomes difficult to provide effective data writing/erasing.